Electronic component and panel for producing the same

ABSTRACT

One embodiment of the invention relates to an electronic component having stacked semiconductor chips, and to a panel for production of the component. In one case, the stack has a flat conductor structure with a chip island on which a stacked semiconductor chip is arranged, while a first semiconductor chip is located underneath it. The chip island is surrounded by flat conductors which have contact pillars. These contact pillars have pillar contact pads which, together with the active upper face of the first semiconductor chip and the upper face areas of a plastic encapsulation compound form a coplanar overall upper face.

BACKGROUND

One embodiment of the invention relates to an electronic componenthaving stacked semiconductor chips, and to a panel for production of thecomponent.

The stacking of semiconductor chips of different size to form a compactelectronic component is costly and is associated with high risksrelating to correct interaction of the integrated circuits of thesemiconductor chips. The high costs are incurred, in particular as aresult of the provision of wiring layers or rewiring layers for each ofthe semiconductor chips to be stacked, and by the production ofelectrical connections between the wiring layers of each semiconductorchip. Furthermore, electrical connections must be created leading fromthe various wiring layers to outer contacts of an electronic componentfor surface mounting.

SUMMARY

One embodiment of the invention specifies an electronic component thatcan be produced at low cost, has stacked semiconductor chips and allowscorrect interaction of the stacked semiconductor chips and low-ostelectrical connection of the contact pads of the semiconductor chips toouter contacts of the electronic component for surface mounting.

According to one embodiment of the invention, an electronic component isspecified which has a stack of semiconductor chips. The stack includesat least one first semiconductor chip and a stacked second semiconductorchip. The semiconductor chips themselves include an active upper facewith contact pads to their integrated circuits, and a rear face.Furthermore, a flat conductor structure with a chip island and flatconductors surrounding the chip island is arranged in the electroniccomponent. Contact pillars on the flat conductors are alignedorthogonally with respect to the flat conductors.

The stacked second semiconductor chip is fixed by its rear face on thechip island of the flat conductor structure, and its contact pads areelectrically connected via bonding wires to the flat conductors whichsurround the chip island. The first semiconductor chip is arrangedunderneath the chip island, and is surrounded by the contact pillars ofthe flat conductor structure. The flat conductor structure with the chipisland and the stacked second semiconductor chip applied to it, as wellas the bonding connections and the flat conductors which surround thechip island, as well as the outer surfaces of the contact pillars areembedded in a plastic encapsulation compound. The first semiconductorchip is likewise surrounded on its rear face and on its edge faces bythe plastic encapsulation compound, and is arranged in the plasticencapsulation compound in such a way that its active upper face isaligned to be coplanar with respect to the upper face areas of theplastic encapsulation compound, and to be coplanar with respect topillar surfaces of the contact pillars, with the upper faces which arealigned to be coplanar forming an overall upper face. In this context,the base surfaces of the contact pillars are referred to as pillarcontact pads.

This overall upper face offers the capability to access the contact padsof the first semiconductor chip as well as the contact pads of thestacked second semiconductor chip via the contact pillars, the flatconductors and the bonding connections. Only one wiring layer isrequired on the overall upper face for this purpose, and electricallyconnects the semiconductor chips to one another via wiring lines.

One embodiment of the invention thus combines a specifically developedflat conductor structure which has metallic contact pillars, with auniversal package structure to form an electronic component with stackedsemiconductor chips. The pillar structures of the flat conductorstructure allow through contacts to be produced. This results in pillarcontact pads arranged flat on the overall upper face, and contact padsfor the first semiconductor chip, which can then be electricallyconnected at low cost by means of microstructured wiring.

In this case, the mounting of the first semiconductor chip on a carrierwith adhesive bonding on one side and the mounting of the stacked secondsemiconductor chip on the chip island of the flat conductor structurecan be carried out very largely separately, thus minimizing theinstallation risk. Furthermore, the electronic component does not havean expensive multilayer substrate, but only a single wiring layer, whichis arranged on the overall upper face. Semiconductor chips with adifferent design can thus be flexibly combined and stacked one on top ofthe other for the electronic component according to the invention, withidentical semiconductor chips, or semiconductor chips of the same size,not being precluded.

The vertical through contacting through the plastic encapsulationcompound to the overall upper face with the aid of the contact pillarsof the flat conductor structure is produced at low cost. In this case,before application of the wiring layer, the pillar contact pads of thecontact pillars remain, via which the contact pads of the stacked secondsemiconductor chip are connected, and the contact pads of the firstsemiconductor chip, which is arranged underneath the chip island, arevisible so that wiring is made simpler by means of a wiring layer whichis used by both stacked semiconductor chips.

In one embodiment, the wiring layer may have a wiring level which isarranged on the overall upper face and has outer contact pads. Theseouter contact pads are electrically connected via the wiring lines topillar contact pads on the upper faces of the contact pillars, and/or tothe contact pads of the first semiconductor chip. In this case, onewiring level is completely sufficient to provide electrical access toboth semiconductor chips, for correct interaction of the stackedsemiconductor chips.

In one embodiment, solder balls and/or stud bumps can be arranged asouter contacts on the outer contact pads. In this case, anapplication-specific form of outer contacts can be provided on the outercontact pads.

One embodiment of the invention relates to a panel which has a leadframewith component positions arranged in rows and columns. Electroniccomponents which are already complete can be provided, with the stackedsemiconductor chips, at the component positions on a panel such as this,and the outer contacts for each of the electronic components can alsoalready be fitted on the panel. A panel such as this reduces the priceof production of electronic components with stacked semiconductor chipsaccording to one embodiment of the invention, thus allowing electroniccomponents to be produced at low cost.

The shape of the panel may correspond, in its extent and extentmarkings, to a standard semiconductor wafer. In this case, methodtechniques that have been proven useful for semiconductor wafers canalso be carried out successfully with a “wafer panel” such as this.

One embodiment of a method for production of a panel for two or moreelectronic components includes the following method steps. First, aleadframe is produced, with component positions arranged in rows andcolumns. In this case, a component position includes a chip island andflat conductors surrounding the chip island. Contact pillars arearranged on the flat conductors and are aligned orthogonally withrespect to the flat conductors. A leadframe such as this with chipislands, flat conductors and contact pillars arranged on them can beproduced by structure etching of a metal plate composed of a copperalloy or of a bronze alloy, or by stamping a metal foil, at low cost.

Once a leadframe such as this is available, a semiconductor chip to bestacked is fitted at the component positions on the chip islands. Bondconnections are then produced between flat conductors which surround thechip island and the contact pads on active upper faces of the stackedsemiconductor chips. A bonding wire technique which makes use of bondingwires composed of a gold or an aluminum alloy is suitable for productionof such bond connections.

Irrespective of the time at which the leadframe is fitted with stackedsecond semiconductor chips, first semiconductor chips can be fitted withtheir active upper faces to a carrier with adhesive bonding on one side.For this purpose, the semiconductor chips are arranged in rows andcolumns which correspond to the rows and columns of the componentpositions on the leadframe. The leadframe with the stacked secondsemiconductor chip is then applied and aligned to the carrier, withadhesive bonding on one side, with semiconductor chips arranged in rowsand columns, in such a way that the first semiconductor chips arearranged underneath the chip islands, and are surrounded by contactpillars.

The base surfaces or pillar contact pads of these contact pillars arepositioned on the carrier, with adhesive bonding on one side, and arethus aligned in a coplanar form on a common plane with the active upperfaces and the contact pads of the first semiconductor chip.

Next, the leadframe with stacked semiconductor chips and bondconnections is then embedded in a plastic encapsulation compound to forma composite panel on the carrier. Once the plastic encapsulationcompound has cured, the composite panel is self-supporting and thecarrier can be removed exposing an overall upper face composed of activeupper faces of the first semiconductor chips, pillar contact pads of theplastic pillars, and an upper face of the plastic compound. A wiringlayer is then applied to the overall upper face, forming wiring linesand outer contact pads on the composite body. During this process, thewiring lines connect the outer contact pads to the contact pads of thefirst semiconductor chip and/or to the pillar contact pads of thecontact pillars.

One embodiment of this method results in a panel with two or morecomponents by means of a single molding process, and only a singlewiring layer is required in order to connect the stacked semiconductorchips and their integrated circuits to one another, and to connect themto outer contact pads. Outer contacts can then be applied to the outercontact pads without having to separate the panel into individualcomponents at this stage. The panel then just needs to be separated inorder to produce individual electronic components, which can be done bysawing along the saw tracks between the component positions, which arearranged in rows and columns.

It is also possible to provide the outer contact pads on an electroniccomponent with outer contacts only after the panel has been separatedinto individual electronic components. This may be used in many caseswhen different forms of outer contacts are required for differentapplications.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 illustrates a schematic cross section through an electroniccomponent, according to one embodiment of the invention.

FIG. 2 illustrates a schematic cross section through a leadframe withfour component positions for production of components as illustrated inFIG. 1.

FIG. 3 illustrates a schematic cross section through the leadframe asillustrated in FIG. 2, fitted with a second stacked semiconductor chipin the component positions.

FIG. 4 illustrates a schematic cross section through a carrier withadhesive bonding on one side and with first semiconductor chips.

FIG. 5 illustrates a schematic cross section through the leadframeillustrated in FIG. 3, which has been fitted on the carrier, withadhesive bonding on one side, as illustrated in FIG. 4.

FIG. 6 illustrates a schematic cross section through a composite bodyformed from a plastic encapsulation compound with an embedded leadframe,as well as first and second semiconductor chips.

FIG. 7 illustrates a schematic cross section corresponding to FIG. 6with a wiring layer fitted and outer contacts applied, on an overallupper face of the panel.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments of the present invention can be positioned ina number of different orientations, the directional terminology is usedfor purposes of illustration and is in no way limiting. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

FIG. 1 illustrates a schematic cross section through an electroniccomponent 1, according to one embodiment of the invention. Theelectronic component 1 has a stack 2 including a first semiconductorchip 3 and a stacked second semiconductor chip 4. The semiconductorchips 3 and 4 have active upper faces 5 with contact pads 6. A rear face7 of the stacked second semiconductor chip 4 is arranged on a chipisland 9. The chip island 9 is part of a flat conductor structure 8which surrounds the chip island 9 with flat conductors 10. Bondconnections 12 extend from the contact pads 6 of the stacked secondsemiconductor chip 4 to the flat conductors 10. The flat conductors 10extend as far as the edge faces 29 and 30 of the electronic component 1.

The flat conductors 10 have contact pillars 11, which are arrangedorthogonally with respect to the flat conductors 10. The contact pillars11 extend as far as an overall upper face 16, which is formed from theactive upper face 5 of the first semiconductor chip 3, pillar contactpads 13 of the contact pillars 11, and an upper face area 14 of aplastic encapsulation compound 15. The flat conductor structure 8, thebond connections 12 and the stacked second semiconductor chip 4 areembedded in the plastic encapsulation compound. The first semiconductorchip 3 is arranged underneath the chip island 9, in such a way that itsactive upper face 5 together with the contact pads 6 forms an overallupper face with the pillar contact pads 13 of the contact pillars 11 andwith upper face areas of the plastic encapsulation compound 15.

The plastic encapsulation compound 15 embeds the flat conductorstructure 8, the bond connections 12, the stacked second semiconductorchip 4, as well as the rear face 7 of the first semiconductor chip 3 andthe edge faces 31 and 32 of the first semiconductor chip. A three-levelwiring layer 17 is arranged on the overall upper face 16. An insulationlayer 33 with through contacts 34 is arranged directly on the overallupper face. The through contacts 34 are electrically connected to thecontact pads 6 of the first semiconductor chip 3 and to the pillarcontact pads 13 of the contact pillars 11. As the next level, the wiringlayer 17 has a wiring level 19, which is in the form of a structuredmetal layer, and has wiring lines 18 as well as outer contact surfaces20. The wiring lines 18 connect the outer contact pads 20 to one anotherand, via the through contacts 34, to the contact pads 6 of the firstsemiconductor chip 3 and to the pillar contact pads 13 of the contactpillars 11, which are themselves electrically connected via the flatconductors 10 and via the bonding wires 12 to the contact pads 6 of thestacked second semiconductor chip 4. As a third level, a solder resistlayer 37 is arranged on the wiring level 19, protects the wiring lines18 and leaves only the outer contact pads 20 free. Solder balls 21 arearranged on the outer contact pads 20, as outer contacts 28 for theelectronic component 1.

An electronic component such as this can be produced at low cost fromone panel in a small number of method steps that will be explained withreference to FIGS. 2 to 7, which illustrate intermediate products ofindividual method steps.

FIG. 2 illustrates a schematic cross section through a leadframe 22 withfour component positions 24 for production of components as illustratedin FIG. 1. Sawing along the dashed-dotted line 35 results in the flatconductor structure 8, which is illustrated in FIG. 1 and is embedded inthe plastic compound. The component positions 24 are arranged in rowsand columns, so that a leadframe such as this provides two or more flatconductor structures 8.

A component position 24 in the leadframe 22 has a chip island 9 which issurrounded by flat conductors 10, with the chip island 9 being held inposition by means of flat conductor webs 36. Contact pillars 11 areintegrally connected to the flat conductors 10, are aligned orthogonallywith respect to the flat conductors 10, and have a pillar contact pad13. In one embodiment, the length of these contact pillars 11 is between0.1 and 0.9 mm. The contact pillars 11 ensure that there is sufficientheight underneath the chip island 9 to arrange a first semiconductorchip there.

FIG. 3 illustrates a schematic cross section through the leadframe 22 asillustrated in FIG. 2, fitted with second stacked semiconductor chips 4,in the component positions 24. The semiconductor chips 4 are fixed bytheir rear faces 7 on the chip islands 9 by means of a conductiveadhesive or by means of a eutectic solder. The contact pads 6 on theactive upper face 5 of the stacked second semiconductor chip 4 areconnected via gold-alloy bonding wires 12 to the flat conductors 10. Forthis purpose, the flat conductors 10 have a coating, which can bebonded, on the bonding surfaces and/or on the touching surfaces of thebonding wire connections 12. The pillar contact pads 13 of the contactpillars 11 are thus electrically connected via the flat conductors 10and the bonding wire connections 12 to the contact pads 6 of theintegrated circuit of the stacked second semiconductor chip 4.

While the leadframe 22 is fitted with the second semiconductor chip 4and is connected by means of bonding wire connections 12, firstsemiconductor chips are arranged on a carrier, with adhesive bonding onone side and is illustrated in FIG. 4. First semiconductor chips 3 arearranged on a carrier 25, as is illustrated in FIG. 4, irrespective ofthe time of production and fitting of the leadframe 22.

FIG. 4 illustrates a schematic cross section through a carrier 25 withadhesive bonding on one side and with first semiconductor chips 3. Forthis purpose, the active upper faces 5 of the first semiconductor chips3 are adhesively bonded by their contact pads 6 to the adhesive face ofthe carrier 25. The rear faces 7 of the semiconductor chips 3 as well asthe edge faces 31 and 32 of the first semiconductor chips 3 are freelyaccessible. The first semiconductor chips 3 are arranged on the carrier25 in rows and columns corresponding to the rows and columns of thecomponent positions 24 on the leadframe, as is illustrated in FIGS. 2and 3.

FIG. 5 illustrated a schematic cross section through the leadframe 22illustrated in FIG. 3, which is fixed by its pillar contact pads 13 onthe carrier 25, with adhesive bonding on one side, as illustrated inFIG. 4. For this purpose, the pillar contact pads 13 of the contactpillars 11 are adhesively bonded to the adhesive face of the carrier 25in such a way that the contact pillars 11 surround the firstsemiconductor chip 3 on the carrier 25, and the chip island 9 is alignedwith the stacked second semiconductor chip 4 above the firstsemiconductor chip 3. The length of the contact pillar 11 in this casedepends on the thickness of the first semiconductor chip 3 which, inthis embodiment of the invention, is 100 μm, since the firstsemiconductor chip 3 is a thinly ground semiconductor chip. However,thicker semiconductor chips may also be used, since the length of thecontact pillars 11 may be varied between 0.1 and 0.9 mm for a leadframethat has been structured by etching.

FIG. 6 illustrates a schematic cross section through a composite body 27formed from a plastic compound 26 with an embedded leadframe 22, as wellas embedded first and second semiconductor chips 3 and 4. Only onemolding process on the carrier 25 is required to embed the structure asillustrated in FIG. 5 in a plastic compound 26. Once the plasticcompound 26 has cured, the carrier 25 is removed, and the overall upperface 16 of the self-supporting composite body 27 is exposed. Thedelamination of the carrier 25 from the composite body 27 can beachieved by heating the adhesive layer between the carrier and theoverall upper face 16, assuming that a thermoplastic is used as theadhesive. The carrier 25 is in this case removed by pulling the carrieroff the composite body 27 at the side, when a rigid carrier 25, withadhesive bonding on one side, is used. The carrier 25 can be rolled offwhen a film is used as the carrier with adhesive bonding on one side. Awiring layer is applied to the overall upper face 16, which has now beenexposed, in order to connect the first semiconductor chip 3 to thestacked second semiconductor chip 4.

FIG. 7 illustrated a schematic cross section corresponding to FIG. 6with a wiring layer 17 fitted and outer contacts 28 applied on anoverall upper face 16 of the panel 23. The fitting of the wiring layer17, which itself has three levels, is carried out successively byfitting and structuring of the three levels. For this purpose, a firstinsulation layer 33 has through contacts 34, which are connected to thepillar contact pads 13 of the contact pillars 11, and to the contactpads 6 of the first semiconductor chip 3. As a further level, astructured metal layer is arranged as a wiring level 19 in the wiringlayer 17. This wiring level 17 has wiring lines 18 between outer contactpads 20 and through contacts 34.

A solder resist layer 37 is applied as a third level of the wiring layer17, leaving only the outer contact pads of the wiring level 19 free. Inthis embodiment of the invention, solder balls are applied as outercontacts 28 to the exposed outer contact pads 20.

A panel 23 formed in this way with component positions 24 has a stack 2including a first and a second semiconductor chip 3 and 4 at thecomponent positions 24, and can be separated along the dashed-dottedline 35, once the outer contacts 28 have been fitted, in order to formindividual components.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

1. (canceled)
 10. An electronic component comprising: a stack ofsemiconductor chips having a first semiconductor chip and a stackedsecond semiconductor chip, the semiconductor chips having an activeupper face with contact pads to integrated circuits and a rear face; aflat conductor structure having a chip island, flat conductorssurrounding the chip island, and contact pillars arranged on the flatconductors and aligned orthogonally with respect to the flat conductors;wherein the second semiconductor chip is arranged with its rear face onthe chip island and wherein its contact pads are electrically connectedvia bonding wire connections to the flat conductors; wherein the firstsemiconductor chip is surrounded by the contact pillars and is arrangedunderneath the chip island such that pillar contact pads of the contactpillars, upper face areas of a plastic encapsulation compound thatembeds the semiconductor chips, the contact pillars and the flatconductor structure, and the active upper face of the firstsemiconductor chip, form an overall upper face, and wherein a wiringlayer is arranged on the overall upper face and electrically connectsthe semiconductor chips to one another via wiring lines.
 11. Theelectronic component of claim 10, wherein the wiring layer comprises awiring level arranged on the overall upper face and comprises outercontact pads that are electrically connected via the wiring lines to thepillar contact pads of the contact pillars, and/or to the contact padson the first semiconductor chip.
 12. The electronic component of claim10, wherein solder balls are arranged on the outer contact pads.
 13. Theelectronic component of claim 1 configured within a panel comprising aleadframe with additional electronic components arranged in rows andcolumns.
 14. The electronic component of claim 13, wherein the shape ofthe panel corresponds in its extent and extent markings to a standardsemiconductor wafer.
 15. A method for production of a panel for aplurality of electronic components producing leadframe with componentpositions arranged in rows and columns, whereby a component positioncomprises a chip island and flat conductors which surround the chipisland, as well as contact pillars, which are arranged on the flatconductors and are aligned orthogonally with respect to the flatconductors; applying a stacked semiconductor chip to the chip island ofthe component positions; producing bonding wire connections between theflat conductors and contact pads on active upper faces of the stackedsemiconductor chips; applying first semiconductor chips with theiractive upper faces to a carrier with adhesive bonding on one side, withthe first semiconductor chips being arranged in rows and columns whichcorrespond to the rows and columns of the component positions; applyingthe leadframe with stacked semiconductor chips to the carrier in such away that the contact pillars of the leadframe are adhesively bonded bytheir upper faces to the carrier and the first semiconductor chips arearranged on the carrier underneath the chip islands of the leadframe andare surrounded by contact pillars; embedding the leadframe with stackedsemiconductor chips and bonding wire connections in a plastic compoundto form a composite body on the carrier; removing the carrier exposingan overall upper face composed of active upper faces of the firstsemiconductor chips, pillar contact pads of the contact pillars, and anupper face of the plastic compound; applying a wiring layer to theoverall upper face, forming wiring lines and outer contact pads; andwherein the wiring lines connect the outer contact pads to the contactpads of the first semiconductor chip, and/or to the pillar contact padsof the contact pillars.
 16. The method of claim 15 further comprisingapplying solder balls to the outer contact pads to provide outercontacts.
 17. The method of claim 15 further comprising separating thepanel into individual electronic components.
 18. The method of claim 17further comprising applying outer contact pads of an electroniccomponent.
 19. An electronic component comprising: a first semiconductorchip having an active upper face, contact pads, and a rear face; astacked second conductor chip having an active upper face, contact pads,and a rear face; a chip island; flat conductors surrounding the chipisland; contact pillars arranged on the flat conductors and surroundingthe first semiconductor chip; wherein the second semiconductor chip isarranged with its rear face on the chip island; means for electricallyconnecting the contact pads of the second semiconductor chip to the flatconnectors; a plastic encapsulation compound configured to embedd thefirst and second semiconductor chips, the contact pillars, the chipisland, and the flat conductors; wherein the first semiconductor chip isarranged under the chip island such that pillar contact pads of thecontact pillars, upper face areas of the plastic encapsulation compound,and the active upper face of the first semiconductor chip form anoverall upper face; and means on the overall upper face for electricallyconnecting the first and second semiconductor chips to each other. 20.The electronic component of claim 19, wherein the contact pads of thesecond semiconductor chip are electrically connected to the floatconnectors via bonding wire connections.
 21. The electronic component ofclaim 19 further comprising a wiring layer arranged on the overall upperface and electrically connecting the first and second semiconductorchips to each other via wiring lines.
 22. The electronic component ofclaim 21, wherein the wiring layer comprises a wiring level arranged onthe overall upper face and comprises outer contact pads that areelectrically connected via the wiring lines to the pillar contact padsof the contact pillars and to the contact pads on the firstsemiconductor chip.
 23. The electronic component of claim 19, whereinsolder balls are arranged on the out contact pads.
 24. The electroniccomponent of claim 19 configured with a panel comprising a leadframewith additional electronic components arranged in rows and columns. 25.The electronic component of claim 24, wherein the shaped of the panelcorresponds in its extent and extent markings to a standardsemiconductor wafer.